Ramtin Zand from the University of Central Florida (UCF), Orlando, will give a talk on Wednesday April 3, 2019 in the Storey Innovation Center (Room 2277) from 10:15 am - 11:15 am. Benefits of alternatives to von-Neumann architectures for emerging applications such as neuromorphic computing include avoidance of the processor-memory bottleneck, reduced energy consumption, and area-sparing computation. However, viable solutions to the challenge of designing theses emerging computing systems span the interrelated fields of machine learning, computer architecture, circuit design, and the potential to leverage the complementary characteristics of emerging device technologies. The objective of this research is to exploit technology-specific advantages to advance new transformative opportunities for leveraging the cooperating benefits of well-established CMOS devices, while simultaneously embracing the strengths of emerging technologies. Moreover, an orthogonal dimension of technology heterogeneity is also non-determinism enabled by either low-voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Thus, we leverage the new and powerful prospect of technology heterogeneity both at design-time and at run-time to develop energy-efficient and reliability-aware computing systems. Herein, consider the probabilistic spin logic "p-bit" device as a fabric element comprising a crossbar-structured resistive weighted array. Programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array's weighted connections. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a low-energy Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n _ m 1 _ m 2 _ ... _ m i weighted array as a configurable hardware circuit with an n-input layer followed by i _ 1 hidden layers. Cross-layer simulations indicate that the proposed design can achieve approximately three orders of magnitude reduction in energy consumption compared to the most energy-efficient CMOS-only designs, while realizing at least 90X device count reduction for considerable area savings. This area of research provides several possibilities for future work, such as: 1) leveraging evolutionary algorithm-based optimization methodologies to explore the neuromorphic hardware design space in various architecture-to-device granularities to realize an optimized circuit-level implementation of Deep Neural Networks, and 2) realizing robust stochastic neuromorphic architectures with a natural defense mechanism against various types of adversarial attacks. Biography Ramtin Zand received his M.Sc. degree in Digital Electronics from Sharif University of Technology, Tehran, Iran, in 2012. He is a Ph.D. Candidate in Computer Engineering at the University of Central Florida (UCF), Orlando, FL, with the graduation date of May 2019. He has five years of industry experience as Senior Hardware Design Engineer and is currently a senior Graduate Research Assistant of an NSF and SRC jointlysupported project of the Energy-Efficient Computing from Devices to Architectures (E2CDA) program. He has authored or co-authored 17 conference proceedings papers, 13 journal articles (8 Transactions), and one book chapter, and received research recognition from ACM/IEEE including a best paper recognition at ACM GLSVLSI and a featured paper of the issue in IEEE Transactions on Emerging Topics in Computing (TETC) in 2018. Ramtin is the recipient of the Daniel D. Hammond scholarship and the Alireza Seyedi Doctoral Research Innovation Endowed Scholarship. He is a Student Member of IEEE and a reviewer for various IEEE Transactions and conferences. His research interests include: Machine Learning and Neuromorphic Computing, Emerging Nanoscale Electronics including Spin-based Devices, Reconfigurable and Adaptive Computer Architectures, and Low-Power and Reliability-Aware VLSI Circuits.