High-Level Synthesis of a Genomic Search Engine, ReConFig 2016, Dec. 2016






Accuracy, Cost and Performance Tradeoffs for Floating Point Accumulation, ReConFig 2013, Dec. 2013






Power Efficient, Scalable Hybrid DSP+ARM+FPGA Platform for Computer Vision Tasks, Supercomputing 2013, Nov. 2013






Heterogeneous and Reconfigurable Computing Group (SC09)






A Cluster-On-A-Chip Architecture For High Throughput Phylogeny Search (SEAGEP09)






Exploiting Symmetry to Speed Up FPGA Accelerated Conjugate Gradient (FCCM09)






Aggressive Network Interface And Router Designs For Special Purpose Scalable Distributed Processing Systems (Student Shaun Gause), USC Discovery Day 2007






Predictive Load Balancing for Interconnected FPGAs: FPL2006






Area, Power, and Pin Efficient Bus Transceiver Using Multi-Bit-Differential Signaling: ISCAS2005






Multi-Bit Differential Signaling (MBDS) for Next Generation Off-Chip Interconnect: DAC2004






Next Generation High Speed Board-Level Interconnect Using Fixed-Load Drivers: CS Department






Optoelectronic Multi-Chip Modules: OC2003






Optoelectronic Multi-Chip Module Demonstration System Using Fiber Image Guide Interconnections: CS Department