SHF: Small: Cross-Layer Design Automation for In-Memory Analog Computing (2024-2027)
The project spans various layers of design abstraction, encompassing circuit, architecture, and computer-aided design tools. It addresses several critical aspects, including (1) the development of a novel in-memory analog computing (IMAC) architecture that realizes both matrix multiplication and nonlinear vector operations in the analog domain, (2) the design of a hierarchical analog network-on-chip to support the deployment of large ML workloads on IMAC architecture with minimal need for signal conversion from the analog domain to digital and vice versa, (3) heterogeneous integration of IMAC with existing ML hardware platforms enabling fine-grained function mapping of targeted applications on the developed heterogeneous systems, and (4) development of a fast and accurate simulation framework, incorporating lightweight solvers specifically designed to solve the nodal conductance matrices of memristive crossbars in IMAC architecture.
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