January 12 (Mon), 2009 Notebook computer was used for notes. A pdf transcript of the notes is linked to the course web site. Administrative information: textbook, syllabus, place in curricula. The gate level. Digital circuits: combinatorial and sequential. Binary numbers.
January 14 (Wed), 2009 Quiz 1 (Q1). Unary numbers (tallying). Numbers vs. numerals. Positional notation. Expansion of non-negative binary numbers into power series to convert them to decimal numbers. General formula for conversion of a number from base b to base B. (Example to be completed.)
January 16 (Fri), 2009 Q2. General formula for conversion of a number from base b to base B, with a detailed example (140 decimal to binary). Addition and multiplication of binary integers. Conversion of a number from base b to base B using repeated divisions by base B. Detailed example of conversion of a decimal number to binary number (752 decimal to binary).
January 21 (Wed), 2009 HW1 is due on Monday, January 26. See course web site for the assignment and related instructions. No quiz. Addition and multiplication of binary integers. Conversion of fractions from one base to another, with detailed examples of conversion from decimal to binary. Division of binary numbers.
January 23 (Fri), 2009 HW1 is due on Monday, January 26. See course web site for the assignment and related instructions. Q3. Conversion to hexadecimal and octal from binary by grouping. Conversion to heaxadecimal from decimal by repeated division. Conversion from hexadecimal and octal to decimal using positional notation. Binary subtraction with borrowing.
January 26 (Mon), 2009 HW1 collected. Discussion of all exercises with solutions explanined in class.
January 28 (Wed), 2009 HW1 returned and discussed. Complement notation for negative numbers and arithmetic using complement notation: 10's complement and 9's complement for decimal numbers with examples; 2's complement and 1's complement for binary numbers. Table of numbers from -4 to +3 in sign-magnitude, 2's complement, and 1's complement notation.
January 30 (Fri), 2009 No quiz. Table of numbers from -8 to +7 in sign-magnitude, 2's complement, and 1's complement notation. How to find the 1's complement of a number of n bits quickly. How to find the 2's complement of a number of n bits quickly: two algorithms. Addition of 2's complement numbers: introduction.
February 2 (Mon), 2009 Q4. Answers explained in great detail. HW2 assigned, due Friday, February 6. Test 1 will be on Monday, February 16, 2009. Description on the main page of the course web site: Test 1 will be on Monday, February 16, one week before the last date to withdraw with a grade of W instead of WF. Test conditions: Closed book, No notes, No calculators, Hex binary 0000 to 1111 provided, Page 52 of text included (Boolean algebra formulas), 50 minute time limit (late arrivals will be given up to 10 minutes of extra time). Chapter 1 of textbook completed.
February 4 (Wed), 2009 Q5. Answers explained in great detail. Boolean algebra--started. Variables, literals, AND, OR, NOT.
February 6 (Fri), 2009 No quiz. HW2 collected and corrected. Boolean algebra. Switches. Series and parallel circuits of switches and the equivalent AND-OR circuits. From circuits to expressions.
February 9 (Mon), 2009 No quiz. HW2 returned. HW3 assigned: see http://www.cse.sc.edu/~mgv/csce211sp09/hw/homework3.htm Boolean algebra: basic theorems (sect. 2.4). commutative, associative, and distributive laws (2.5), simplification theorems (started; 2.6)
February 11 (Wed), 2009 No quiz. Chapter 2 completed. Review of laws and theorems of Boolean Algebra on p.52. Chapter 3. Minterm and maxterm expansions: sections 4.2, 4.3, 4.4.
February 13 (Fri), 2009 No quiz. HW3 collected and corrected. Test 1 will be next Monday, February 16.
February 16 (Mon), 2009 Test 1.
February 18 (Wed), 2009 Test 1 returned. Correction of Test 1.
February 20 (Fri), 2009 Quiz 6. Topics from Ch.4, up to p.93.
February 23 (Mon), 2009 Three-minute survey. Circuit kits distributed. Review of circuit kit parts list. Discussion of the circuit in which an LED circuit is "buffer-driven" by an inverter. (Schematics are online on the web site.) Connection of power busses, as detailed on the Circuit 1 description on the web site (six steps under "Power Busses") completed.
February 25 (Wed), 2009 Circuit 1 through step 15 completed ("Power Busses," "LED Test," start of "Inverter-LED Test"). Students who were not in class on Monday are helped in catching up by students who were (thanks!).
February 27 (Fri), 2009 Circuit 1 through step 23. The rest of the work is to be done by the students in their own time. Design of incompletely specified functions (Section 4.5 text). Design of an adder started (section 4.7 text).
March 2 (Mon), 2009 Discussion of Circuit 1 requirements. As indicated on the main page of the course web site, Circuit 1 needs to be brought in on Wednesday for check-off. A report needs to be turned in at that time. HW4 due date is moved to Monday, March 9. Design of full adder completed (section 4.7). Karnaugh maps started (chapter 5: section 5.1 and start of section 5.2).
March 4 (Wed), 2009 Circuit 1 checked and report collected. HW4 due date moved to Monday, March 16 (due to spring break), with possible delay to March 18. Karnaugh maps of three variables.
March 6 (Fri), 2009 HW4 date moved to Friday, March 20, 2009. Karnaugh maps of four variables.
March 16 (Mon), 2009 Karnaugh maps of four variables. Prime implicants, essential prime implicants, don's cares. Examples.
March 18 (Wed), 2009 Reminder: HW4 due on Friday. More examples of how to obtain a minimum sum of products from a Karnaugh maps. Unit 5 of the textbook completed.
March 20 (Fri), 2009 HW4 collected. Circuit 2 assigned, due March 30, 2009 (Monday). HW4 corrected in class.
March 23 (Mon), 2009 HW4 returned. Last exercise (5.21(b)) reviewed carefully, because many students had difficulty doing it. Reminder: Circuit 2 due March 30. Ch.7 of textbook ("Multi-Level Gate Circuits; NAND and NOR Gates") through the beginning of Section 7.2.
March 25 (Wed), 2009 Ch. 7 textbook through section 7.3, with some topics from 7.5. Discussion of Circuit 2 assignment, including design of NAND-NAND Boolean circuit for F'.
March 27 (Fri), 2009 Q7. Reminder: Circuit 2 check-off and report due on Monday. Completion of discussion of Circuit 2 assignment, including design of NAND-NAND Boolean circuit for F'.
March 30 (Mon), 2009 Q8. Circuit 2 checked. Some discussion of circuit 2 and its layout.
April 1 (Wed), 2009 More discussion of circuit 2 and its layout. Quine-McCluskey algorithm (basics and example).
April 3 (Fri), 2009 HW5 assigned, due Wednesday, April 8. More discussion of circuit 2 and its layout. Quine-McCluskey algorith: Patrick's method. Chapter 9 started: Multiplexers.
April 6 (Mon), 2009 HW5 due date postponed to Friday, April 10. Multiplexers and their use to implement circuits. Decoders and demultiplexers.
April 8 (Wed), 2009 Q9. Detailed discussion of HW5, due Friday, April 10.
April 10 (Fri), 2009 HW5 collected and corrected in class. The correction notes are not posted on the web site. More MSI circuits: ROMs and PLAs.
April 13 (Mon), 2009 Take home test 2 handed out in class, due Friday, April 17. HW5 returned. Latches and Flip-Flops chapter started (unit 11): Introduction and the Set-Reset Latch.
April 15 (Wed), 2009 Circuit 3 is due on Wednesday, April 22. Discussion of take-home Test 2. Review of the S-R latch. The gated D latch.
April 17 (Fri), 2009 Circuit 3 is due on Wednesday, April 22. Take-home Test 2 collected. Edge-triggered D Flip-Flop, S-R Flip-Flop, J-K Flip-Flop, T Flip-Flop.
April 20 (Mon), 2009 Circuit 3 is due on Wednesday, April 22. Take-home Test 2 returned, with brief discussion. Registers, with examples of five kinds of them---see class notes. Chapter 13. "Analysis of Clocked Sequential Circuits," started: A Sequential Parity Checker" (Section 13.1).
April 22 (Wed), 2009 Q10. Circuit 3 checked. HW6 assigned, due Monday, April 27. Analysis of Sequential circuits, with two examples that are not in the textbook---see class notes.
April 24 (Wed), 2009 Design of a sequential circuit, from start to end. See class notes.
April 27 (Wed), 2009 HW6 collected. More circuit 3 checked. Discussion of final, which will be at the regularly scheduled time, in the classroom. A few words on equivalence relations (relations that are reflexive, symmetric, and transitive), the partition they induce, and equivalence of states in sequential circuits. Student survey with supplemental questions. End of course. and