Medium-Scale Integrated Circuits

 

Using a 74LS151 (8-to-1 multiplexer) to Implement a Function of Four Variables

 

 

Row

W

X

Y

Z

F(W,X,Y,Z)

Input

0

0

0

0

0

0

 

1

0

0

0

1

0

D0 = 0

2

0

0

1

0

0

 

3

0

0

1

1

1

D1 = Z

4

0

1

0

0

1

 

5

0

1

0

1

0

D2 = Z’

6

0

1

1

0

1

 

7

0

1

1

1

1

D3 = 1

8

1

0

0

0

1

 

9

1

0

0

1

1

D4 = 1

10

1

0

1

0

1

 

11

1

0

1

1

0

D5 = Z’

12

1

1

0

0

0

 

13

1

1

0

1

1

D6 = Z

14

1

1

1

0

0

 

15

1

1

1

1

0

D7 = 0

 

                                                                                74LS151

0 ¡

EN

 

 

Y

S0(LS)

 

 

X

S1

 

 

W

S2(MS)

 

 

 

 

 

 

0

D0

Y-out

  F(W,X,Y,Z)

Z

D1

Y-out

¡ F’(W,X,Y,Z)

Z’

D2

 

 

1

D3

 

 

1

D4

 

 

Z’

D5

 

 

Z

D6

 

 

0

D7

 

 


Using a Decoder to Implement a Function

 

 

Decoder Example 1:

F(X, Y, Z) = PM(0, 2, 3, 5, 7) = Sm(1, 4, 6)

 

Enable the decoder.  Connect input variables X (MS), Y, and Z to address lines A2, A1, and A0.  NAND decoder outputs 1, 4, 6 (this effectively OR’s the min terms of the same number using DeMorgan’s Theorems.)

 

 

                                                        74LS138

 

 

 

 

 

 

 

 

G1

Y0

¡

Y0_L

G2A_L

¡

G2A

Y1

¡

Y1_L

G2B_L

¡

G2B

Y2

¡

Y2_L

 

 

 

Y3

¡

Y3_L

 

 

 

Y4

¡

Y4_L

Z

 

A0 (LS) 

Y5

¡

Y5_L

Y

 

A1

Y6

¡

Y6_L

X

 

A2 (MS)

Y7

¡

Y7_L

 

 

 

 

 

 

 

 

 

Decoder Example 2:

G(X, Y, Z) = PM(0, 3, 4)

 

Enable the decoder.  Connect input variables X (MS), Y, and Z to address lines A2 (MS), A1, and A0.   Use an AND gate to combine decoder outputs 0, 3, 4 (the max terms).