COLLOQUIUM
Department of Computer Science and Engineering
University of South Carolina
 
Network on Chip: A New Direction in System on Chip Design

Partha Pande

Department of Electrical and Computer Engineering
University of British Columbia

Date: March 28, 2005
Time: 1-2PM
Place: Swearingen 1A03 (Faculty Lounge)

Abstract

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an
important trend for System on Chip (SoC) design. The state of the art
has reached a point where commercial designs are readily integrating
in the range of 10-100 embedded functional/storage blocks in a single
SoC. As a result of this enormous degree of integration, several
industrial and academic research groups are striving to develop
efficient communication architectures, in some cases optimized for
specific applications. One of the major problems associated with
future SoC designs arises from non-scalable global wire delays, which
typically increase exponentially or, at best, linearly by inserting
repeaters. Even after repeater insertion, the delay may exceed the
limit of one clock cycle (often, multiple clock cycles). According to
ITRS (2003 update), “Global synchronization becomes prohibitively
costly due to process variability and power dissipation, and
cross-chip signaling can no longer be achieved in a single clock
cycle”. Thus, system design must incorporate networking and
distributed computation paradigms with communication structures
designed first and then functional blocks integrated into the
communication backbone.  
The emerging Network on chip (NoC) design
methodology is a step towards this. The practical implementation and
adoption of the NoC design paradigm is faced with various unsolved
issues related to design methodologies, test strategies, and dedicated
CAD tools. The focus of this seminar is on design aspects and
architectural issues of this new paradigm. The first part presents a
quantitative comparison of various candidate architectures in regards
to data rates, latency, silicon area overhead, and energy
dissipation. This comparison is based on a set of metrics that
establish a useful basis for the optimal evaluation and selection of
interconnect infrastructures for large and complex SoCs.  The second
part focuses on the timing characteristics of NoC
architectures. Through detailed circuit design and timing analysis,
this research has established that different NoC architectures
proposed to date are guaranteed to achieve the high-performance clock
cycle requirements in a given CMOS technology, usually specified in
normalized units of FO4 (Fan out of 4) delays.  The presentation will
conclude with future research directions, namely incorporation of
on-chip error control coding mechanisms, fault tolerant architectures
and test methodologies supporting the NoC paradigm.

Partha Pande is at the verge of finishing his PhD in VLSI design at
the department of Electrical and Computer Engineering, University of
British Columbia. His PhD thesis has evolved around the topic of
“Networks on Chip.” Previously Mr. Pande obtained his M.Sc in
Computer Science from the National University of Singapore in 2001 and
Bachelor degree in Electronics and Communication Engineering from
Calcutta University, India in 1997. After his Bachelor degree he
worked in Industry for a couple of years as Digital System Design
Engineer. At the end of 1999 Mr. Pande came back to academia to pursue
higher studies. Partha Pande obtained several national scholarships
from the Government of India for academic excellence. In addition to
this he received the International Graduate student scholarship from
the National University of Singapore.