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Introduction: Preparation of Standard Cell Library

The purpose of this page is to show you a sample cell library. You cell library will contain these cells and several others.

Example Digital Standard Cell Library

At this point, I have designed a small standard logic cell library. Notice that I have adopted a slightly different naming convention, where I have capitalized the cell names and added a suffix that defines the size of the cell (X1 is minimum size, X2 is double-size, etc.). You should also follow this naming convention because it makes characterization easier. Note that you can rename cells in the Library Manager. When you rename cells, Library Manager will automatically update instances.

Each cell has a schematic, symbol, layout, extracted, and analog_extracted view. Each cell has been successfully verified with DRC and LVS. The schematic and analog_extracted view of each cell has also been simulated using a test bench.

Each cell has all of its pins on a 4.5 um (offset 2.25 grid). These include input pins, output pins, and supply pins.

The cells themselves are all 40.5 um high and a multiple of 13.5 um wide. Both the height and the width are multiples of 4.5 (the global routing grid size).

Also notice that the nwell for each cell meets the sides and top edges of the Vdd rail. This is because Encounter snaps the cells together edge-to-edge. This includes the top and bottom on the cell (instead of overlapping the the rails as shown in tutorial 2).

My library is made up of the following set of cells, although your library will be more complete and include several additional cells.

Cell name	Description
INVX1	Minimal-sized inverter (width_p=6um, width_n=3um)
INVX2	Double-sized inverter (width_p=12um, width_n=6um)
NAND2X1	Minimal-sized 2-input nand (width_p=6um, width_n=3um)
NOR2X1	Minimal-sized 2-input nor (width_p=6um, width_n=3um)
TRISTATEX1	Minimal-sized tranmission gate (not a real tristate buffer) (width_p=6um, width_n=3um)
DFFX1	Rising-edge triggered D-flip-flop (using design from page 22 (Fig. 1.31b) of the textbook)
BUFX1	Tapered buffer cell (used for clock buffering)
FILL	Layout fill cell, used for nwell continuity

The schematic and layout views of these cells are shown below.

INVX1
Schematic
Layout

INVX2
Schematic
Layout

NANDX2
Schematic
Layout

NORX2
Schematic
Layout

TRISTATEX1
Schematic
Layout

DFFX1
Schematic
Layout

BUFX1
Schematic
Layout

FILL
Layout

Important Notes

Take a close look at these cells. There are several things of which you should take note.

• First, notice that I included one body node contact for each transistor in each layout. For example, while the INVX1 layout has two total body contacts, the NAND2X1 gate has four.
• Notice that in the INVX2 schematic I used a multiplicity of two for both the PMOS and NMOS. This made Layout-XL place two minimum-sized FETs when I did a "Create | Pick From Schematic" and LVS required that these FETs be wired in parallel.
• Notice in the INVX2, NAND2X1, and NOR2X1 designs that I used a technique called "transistor chaining" to overlap the drains/sources of adjacent PMOSs and NMOSs . Obviously, you can only do this for pairs of transistors whose drain or source are connected to a common net. Note that you may have to "flip" the FETs in the layout editor (mirror about the Y axis using the device properties) in order to make this work (depending on if the transistors are in parallel or series). The effect of this transistor chaining is smaller (denser) layouts.
• Notice that I had to use pmos4/nmos4 cells in the schematic for the tristate. This was required due to a bug in the design kit/Cadence (if you use the 3-terminal MOSFETs, Layout-XL complains about there not being any vdd or gnd symbols in the schematic, despite the fact that the body terminals are get to vdd! and gnd! in the transistor properties).
• Notice that in the DFFX1 and BUFX1 layout, I placed additional vdd! and gnd! pins in the top-level design (in addition to the supply pins present in the lower-levels of the hieararchy. You can't see them, because they overlap the vdd! and gnd! pins in the cell underneath them. Even for hieararchical designs, make sure all your pins are on the 4.5 um (offset 2.25 um) grid.
• Notice the FILL cell has the minimum width for our routing grid size. In this case, it is exactly 4.5 um wide.

Really Important Note

Finally, notice that for each of these cells, every input and output pin except for vdd! and gnd! is capitalized. This is absolutely critical. On a previous iteration of my example design flow, I neglected to capitalize the CLK pin on the DFF. This caused the place-and-route tool to refuse to route the clock inputs on all the DFFs.